With the increased speed of computers and the need for high performance peripherals, the use of high speed serial data communications applications in integrated circuits built to physically interface to any given bus has also increased. In the past, serial communication was typically regulated to relatively slow applications and components such as computer mice, modems, and the like. However, serial communication is now desired and employed in many areas of communication or data transfer. For example, high speed serial communication is employed for communication or data transfer to digital memory, optical communications, hard drive devices, digital video (e.g., digital video recorders), network devices, compact disk drives, digital video disk drives, digital cameras, and many more devices.
There are several common serial communication standards currently available, including USB (Universal Serial Bus) 1.1 that provides communication speeds up to 12 Mbps (Million bits per second), FireWire (IEEE 1394) that operates at 400 Mbps, and USB 2.0 that operates at a maximum of about 480 Mbps. The operational speeds of these standards have increased over time. For example, the speed of USB 2.0 versus USB 1.1 illustrates an improvement of over 40 times. State of the art optical networks used in data communications and telecommunications operates at bit rates up to 40 Gbps (billion bits per second).
Generally, serial communication includes a transmitter and a receiver. The transmitter encodes or modulates a lower speed parallel data bus into a higher speed serial data stream that is then placed on a communication media. The serial data stream travels on the communication media and is then obtained from the media by the receiver. The serial data stream is then processed by the receiver in order to decode or recover the original data and de-serialize the resulting data into a duplicate parallel data bus.
Several techniques exist to encode the serial data and many signaling approaches can be used to transmit the data. Encoding techniques are used to embed a guaranteed density of transitions in the data and to facilitate reconstruction of the parallel data bus at the receiver. An example of these encoding techniques is 8b-10b encoding used on the physical layer in Gigabit Ethernet, PCI-Express, Fibre Channel, and 1394. Another encoding method is referred to as scrambling, which is used in SONET (Synchronous Optical NETwork). At the lowest level, the signaling approach can be as simple as NRZ (non-return to zero) binary, where 0 bit is encoding as one voltage level and a 1 bit is encoding as a different voltage level. Another commonly employed serial encoding/decoding scheme is (Non-Return-to-Zero Inverted) encoded and bit stuffed. NRZI is a data transmission method in which the polarity of the bit is reversed whenever a 0 bit is encountered, and a static voltage level is transmitted whenever a 1 bit is encountered as illustrated in FIG. 1, and designated at reference numeral 110. NRZI thus uses the presence or absence of a transition to signify a bit (indicating a logical 0 by inverting the state). Combined with bit-stuffing, where an extra 0 bit is inserted after every six consecutive 1 bits, this data encoding causes a guaranteed transition every 7 bit times when a data payload would be all 1 bits. Every transition gives the CDR circuit phase information that it uses to align its recovered clock to the phase of the incoming data. The less time between transitions, the less phase error which is to be expected caused by frequency offset. Finally, the data can be transmitted using a multi-level signaling approach where multiple bits are encoding as multiple data levels and transmitted at a lower data rate. For example, if two bits are wished to be transmitted simultaneously at one half the equivalent data rate as the binary approach, four voltage levels can be assigned to the various bit combinations 00, 01, 10, an 11.
The structure of the data stream follows a specific communications protocol, which defines the rules for sending a block of data (each known as a Protocol Data Unit (PDU)) (e.g., 150 of FIG. 2) from one node in a network to another node. The exchanged PDUs comprises three parts: a sync sequence 160, a packet payload (also known as a Service Data Unit (SDU)) 170, and an End of Packet (EOP) 180. The protocol does not define or constrain the data carried in the payload portion 170 of the data block. The protocol does, however, specify the format of the sync sequence.
The incoming data stream may be at a different frequency than the receiving system. Each side can vary from an ideal frequency within a +/−delta range as limited by a ppm tolerance value or jitter tolerance value defined in a respective industry standard. Often, the source and receive frequencies are slightly different. Regardless of the relative source and destination frequencies, the incoming data stream shows all jitter components of an electrical transmission over a bandwidth limited media (e.g., data dependant cycle to cycle jitter).
Several techniques exist to recover and track the possibly asynchronous data at the inputs to a serial receiver. Because of slight variations in timing, operating frequency, and other non-ideal operating conditions present at sending and receiving ends, the recovered clock can become early or late over time. Generally, the recovered data should be obtained from data samples taken at a center of each bit time of an incoming data stream. However, the recovered data can become corrupted as the recovered clocks drift with respect to the data causes data samples to be taken at inappropriate times of the incoming serial data stream. Accordingly, it would be desirable to have systems and/or methods that monitor and correct recovered clock(s) in order to facilitate data and clock recovery of incoming or received serial data streams.
Two primary classes of clock recovery circuits exist: linear and binary (also called bang-bang). A linear clock and data recovery (CDR) circuit attempts to recover the original transmitting clock and data. A conventional CDR circuit attempts to recover the clock and data by utilizing a phase detector (PD) or alternatively a phase-frequency detector (PFD), and source a charge pump followed by a loop filter and the voltage controlled oscillator (VCO) of a phase locked loop (PLL). The phase detector detects the absolute timing error between the current recovered clock and the timing of the ideal clock and together with the charge pump, generates an error signal proportional to the size of the timing error. This error signal is filtered using a loop filter and used to drive the VCO.
A binary clock recovery system recovers the clock by examining the sign of the phase error between the current recovered clock and the data. If the recovered clock is too early, the clock recovery system delays the clock. If the recovered clock is too late, the clock is advanced.